In a typical electronic memory arrangement, reading from and writing to several memory devices is organized by a controller. Double-data-rate synchronous dynamic random access memory (DDR SDRAM) is an example of such an arrangement. For a write operation, the controller places data on a data bus while indicating, on a command bus, a write command, and indicating, on an address bus, a location on the particular memory device at which the data is to be stored. For a read operation, the controller indicates, on the command bus, a read command, and indicates, on an address bus, a location on the particular memory device from which the data is to be read. The memory device responds to the read command and address by placing the requested read data on the data bus.
In contrast, in an alternative electronic memory arrangement, memory devices are arranged in a ring or loop. Rather than a data bus accessed in parallel, there is a series data connection between a controller and a first memory device in the ring. The data connection may, for example, be a multibit bus. A data signal received at the first memory device on the data connection is passed on to a second memory device on an other data connection and a data signal received at the second memory device on the other data connection is passed on to a third memory device on a further data connection, etc. Thus, the data signal propagates around the ring until the data signal is returned to the controller. In addition to the data signal propagating through the ring, there are additional signals also propagating through the ring: a Command Strobe signal; and a Data Strobe signal.
For a write operation, the controller causes the Command Strobe signal to transition from “0” to “1” to indicate the start of a Command and Write Data Packet. Simultaneously, the controller starts to transmit, on the data connection, a Command and Write Data Packet that includes: a write command indicating a particular memory device and address to which data is to be written followed by the data that is to be written. The controller then causes the Command Strobe signal to transition from “1” to “0” to indicate the end of the Command and Write Data Packet.
For a read operation, the controller causes the Data Strobe signal to transition from “0” to “1” to indicate the start of a Read Data Packet. Simultaneously, the controller starts to transmit, on the data connection, a read data packet that includes: a read command indicating a particular memory device and address from which the data is to be read. The controller then causes the Command Strobe signal to transition from “1” to “0” to indicate the end of the Read Data Packet. Subsequently, the controller causes the Data Strobe signal to transition from “0” to “1” to indicate, to the particular memory device, that the requested read data is be transmitted on the data connection.
In the ring arrangement, a read command primes a memory device for a read data transfer. The length of a read is arbitrary and interruptible since the end of the read data transfer operation is determined by a transition of the Data Strobe signal from “1” to “0”. Similarly, the length of a write is arbitrary and interruptible since the end of the write data transfer operation is determined by a transition of the Command Strobe signal from “1” to “0”.
As discussed, when memory devices are arranged in a ring, packets originate at a controller and flow unidirectionally through a ring of memory devices and back to the controller. Different configurations are possible based on either distributing a clock in parallel or sourcing the clock synchronously along with the data and strobes. The second configuration has more pin overhead than the first configuration based on extra differential clock output pins.
Pin overhead continues to be a carefully monitored quality of interfaces between devices, such as the interface between the controller and the first memory device or between memory devices, with a lower pin overhead being desirable. That is, it is desirable to reduce the ratio of control pins to data pins.